Analog-to-digital converters (ADCs) are in widespread use today in electronic applications for consumer, medical, industrial, etc. Typically, ADCs include circuitry for receiving an analog input signal and outputting a digital value proportional to the analog input signal. This digital value is typically in the form of either a parallel word or a serial digital bit stream. There are many types of analog-to-digital conversion schemes, such as voltage-to-frequency conversion, charge redistribution, delta modulation, as well as others. Typically, each of these conversion schemes has its advantages and disadvantages.
One type of analog-to-digital converter (ADC) that has seen increasing use is the sigma-delta ADC (sigma-delta and delta-sigma will be used interchangeably herein). A sigma-delta modulator typically converts an analog input to a digital serial string of “ones” and “zeros” having an average amplitude over time proportional to the analog input. Sigma-delta modulation generally provides for high accuracy and wide dynamic range as compared to earlier delta modulation techniques. Sigma-delta modulation is often referred to as an oversampled converter architecture and is typically immune from some of the earlier undesirable second order effects of delta modulation.
Each sigma-delta modulator loop includes one or more quantizers that convert the analog incoming signals to a digital output code. For a sigma-delta ADC, these quantizers are low-resolution ADCs, often 1-bit ADC (or comparators). In this case, the sigma-delta modulator is called a 1-bit modulator. If the output of the quantizer has a higher resolution than 1 bit, then the sigma-delta modulator is called a multi-bit modulator and the sigma-delta ADC is called a multi-bit sigma-delta ADC.
In a multi-bit sigma-delta ADC, the output resolution allows more than two digital output levels. If the number of possible output levels (nlev) is a power of 2 (for example nlev=2^M), the output can be encoded into an M-bit word and the modulator is a multi-bit M-bit modulator. However, the number of output levels (nlev) is not necessarily a power of 2 (especially for the low number of levels) and in this case, the modulator can also be called multi-bit or multi-level. For example, 3-level modulators are very popular. If nlev is a power of 2, an equivalent number of bits can be calculated for a multi-level modulator and is given by the formula: M=log2(nlev) where M is the number of equivalent bits. If nlev is not a power of 2, the minimum number of bits required to encode the output is: M=Floor(log2(nlev)).
In a multi-level (or multi-bit) sigma-delta ADC, the quantizer is very often a differential input Flash ADC, composed of nlev−1 comparators in parallel with equidistant thresholds of comparison, placed at (nlev−2k)/(nlev−1)*Vref where k is an integer between 1 and (nlev−1), giving an output on nlev bits coded with a thermometer coding. In that case, the number of distinct output levels is nlev which can be coded into a minimum of Floor(log 2(nlev)) bits. For example, a 3-level modulator quantizer can be a Flash ADC composed of two (2) comparators with thresholds of +Vref/2 and −Vref/2 and the 3-level output words can be encoded into Floor(log2(3))=2 bits. The placement of the thresholds ensures also a uniform quantization which minimizes the quantization error average on the whole input range. In a typical flash ADC implementation, each comparator has its own switched-capacitor input stage in determining its associated voltage threshold, and a thermometer-to-binary encoder at the outputs of the flash comparators for generating the digital words to the sigma-delta modulator loop digital-to-analog converter (DAC), and a digital signal output decimation filter.
All sigma-delta modulators, working in a continuous mode, produce idle tones at their outputs if a certain periodic or direct current (DC) input is provided. These idle tones are due to the quantization process and are inherent in the design of the sigma-delta modulator architecture. In particular, these idle tones depend strongly on the amplitude and frequency of the input signal and are difficult to filter out since they can reside in the base band of the signal to be measured.
These idle tones are unwanted and create undesired behavior at the outputs like undesired high tones in an audio device. These tones limit the spurious free dynamic range (SFDR) and thus the signal-to-noise-and-distortion (SINAD) of the device especially if specific direct current (DC) inputs are provided (that are usually a rational fraction of the quantization step).
Commonly-assigned U.S. Pat. No. 7,961,126, which is hereby incorporated by reference in its entirety as if fully set forth herein, describes an approach using a variable resolution quantizer having automatic dithering for removing undesired idle tones in the digital output of a sigma-delta ADC. In that approach, a multi-bit quantizer changes its output resolution (its number of output levels) at each sample based on a random or pseudo-random resolution sequence. Changing the resolution modifies the quantization function, effectively adding a dither signal at the input of the quantizer. While generally effective, if the resolution sequence takes on resolution values that are too low, the resulting quantization noise may be relatively high.